Job Description

Our client is looking for a Physical Design Engineer (VLSI Design) with a Fulltime project in Mountain View, CA (Hybrid). below is the detailed requirement.

Position : Physical Design Engineer (VLSI Design)

Location : Mountain View, CA (Hybrid)

Mode of hire : FullTime

Job Description:

Summary:

We are looking for a highly skilled Physical Design Engineer with experience in Physical Design, specializing in Place and Route (P&R) and Static Timing Analysis (STA). Responsible for various aspects of the backend VLSI design flow , including floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off verification . The role requires expertise in EDA tools, physical verification methodologies, power optimization, and performance tuning .

Top 3 Skills - PnR, STA and Synthesis with 8-10 yrs of Physical Design Experience

Responsibilities:

Block-Level Physical Design:

• Floor planning & Partitioning Define optimal floorplan with power grid, macro placements, and congestion analysis.
• Strong scripting experience.
• Placement & Optimization Perform standard cell placement, legalization, and optimization to improve area, power, and timing.
• Clock Tree Synthesis (CTS) Design and optimize low-skew, high-performance clock networks .
• Routing & DRC Closure Ensure successful global and detailed routing , meeting design rule constraints.
• Timing Closure Work on setup/hold timing violations , signal integrity, and cross-talk reduction using static timing analysis (STA) .
• Power & IR Drop Analysis Optimize power planning, power integrity (IR drop, EM), and leakage reduction techniques .

Top-Level Physical Design:

• Chip-Level Floor planning & Hierarchical Design Manage top-level layout planning , pin assignments, and cross-block optimizations.
• Strong scripting experience.
• Clock & Power Distribution Design robust clock trees and power delivery networks (PDN) .
• Integration of IP & Sub-blocks Ensure seamless integration of IP blocks and handle complex routing challenges.
• Chip Assembly & Sign-Off Perform final netlist-to-GDSII implementation , addressing physical and electrical verification.

DFT Integration

• Work with Design for Test (DFT) teams to ensure scan chain connectivity and testability

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