DFT Engineer Job at Technical-Link N. America, Maynard, MA

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  • Technical-Link N. America
  • Maynard, MA

Job Description

About the Company

Design intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. This role is within our ASIC team, specifically as part of the Design for Test group.

About the Role

Your Impact

  • You will set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC and SCAN at chip and/or block level and set up pattern generation flow for Scan/ATPG & MBIST/Repair/Fuse.
  • You will work with seasoned DFT engineers to implement and verify DFT.
  • You will also interact with RTL/PD/STA/ATE, collaborating with them for a successful tape out.

Responsibilities

  • Minimum Qualification:
  • BSEE or equivalent with + 8 years of experience or an MSEE or equivalent with + 6 years of experience, or PHD with + 3 years of experience in ASIC DFT flows and Implementation
  • Prior experience implementing scan control logic in RTL
  • Prior experience with hierarchical ATPG and core wrapping techniques, ATPG and post-silicon DVT
  • Prior experience with Synopsys/Mentor DFT tools

Required Skills

  • Experience with scan compression and scan partitioning
  • Experience with MemoryBIST, eFuse, Repair and yield improvement techniques
  • Experience with JTAG Boundary Scan Insertion AC/DC
  • Experience with Clocking architecture during various ATPG modes such as: Intest and Extest
  • TCL scripting experience to automate DFT flows

Preferred Skills

  • 225k per year

Job Tags

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